The present invention relates to a method of generating an ASIC design database, which is important when a large-scale integrated circuit device such as a system LSI is to be designed.
There is known a conventional design method, which uses a database in order to avoid useless repetition at the time of re-designing or disability of design, when a system LSI is to be developed.
In designing an ASIC (Application Specific Integrated Circuit), a designer first analyzes given design specifications, examines architecture candidates, selects a most prospective architecture, and describes the selected architecture using a hardware description language. The act of the describing is called “operation description”. The obtained operation description is an operation-level design result. The operation-level design is verified by applying an operation-level simulator or a verifier to this operation-level design result.
Based on the operation description, the designer then produces an RTL (Register Transfer Level) description in which the object of design is described in a register transfer level. The RTL description is automatically generated from the operation description by means of an operation synthesis tool. The generated RTL description is also based on a hardware description language (HDL). The RT level design is verified by applying an RT level simulation tool, etc. to the RTL description.
Following the verification, a net list (gate-level logic circuit description), in which the object of design is described in a gate level on the basis of the RTL description, is generated by means of a logic synthesis tool. The gate-level design is verified by applying a logic simulation tool, etc. to the net list, following which a floor plan is carried out. In the floor plan for the net list, blocks constituting gate-level logic circuits are generally arranged and wired.
Subsequently, based on the result of the floor plan, the gate-level design represented by the net list is evaluated. Specifically, using the information on the arrangement of blocks constituting logic circuits and the information on the wiring of the blocks, the layout area, timing, power consumption, etc. are calculated.
In general, when the data mentioned above is stored, it is divided into specification data and RTL description data.
The specification data contains data on the process time, layout area, power consumption, test cost, etc.
The RTL description data is an RTL description file in units of an entity.
In the methods of constituting the databases, it is necessary to perform a process for extracting the content of specifications after the design is finished. This results in useless procedures in constituting the database.